NXP Semiconductors

18-bit universal bus transceiver;
3-state. The 74ALVCH16501 is an 18-bit transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. Data flow in each direction is controlled by output enable (OEAB andOEBA), latch enable (LEAB and LEBA), and clock (CPAB and CPBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CPAB is held at a HIGH or LOW logic level. If LEAB is LOW, the A-bus data is stored in the latch/flip-flop on the LOW-to HIGH transition of CPAB. When OEAB is HIGH, the outputs are active. When OEAB is LOW, the outputs are in the high-impedance state.Data flow for B-to-A is similar to that of A-to-B but usesOEBA, LEBA and CPBA. The output enables are complimentary (OEAB is active HIGH, andOEBAis active LOW).To ensure the high-impedance state during power-up or power-down,OEBAshould be tied to VCCthrough a pull-up resistor and OEAB should be tied to GND through a pull-down resistor;
the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver.Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
Warehouse № Lead time Qty Price
7 up to 3 wk. 228 pcs. By request

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